lscpu - AMD Ryzen 5 2600 Six-Core
Architektura: x86_64
Tryb(y) pracy CPU: 32-bit, 64-bit
Address sizes: 43 bits physical, 48 bits virtual
Kolejność bajtów: Little Endian
CPU: 12
Lista aktywnych CPU: 0-11
ID producenta: AuthenticAMD
Nazwa modelu: AMD Ryzen 5 2600 Six-Core Processor
Rodzina CPU: 23
Model: 8
Wątków na rdzeń: 2
Rdzeni na gniazdo: 6
Gniazd: 1
Wersja: 2
Frequency boost: enabled
CPU(s) scaling MHz: 56%
CPU max MHz: 3400,0000
CPU min MHz: 1550,0000
BogoMIPS: 6798,90
Flagi: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb hw_pstate ssbd ibpb vmmcall fsgsbase bmi1 avx2 smep bmi2 rdseed adx smap clflushopt sha_ni xsaveopt xsavec xgetbv1 clzero irperf xsaveerptr arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif overflow_recov succor smca sev sev_es
Wirtualizacja: AMD-V
Cache L1d: 192 KiB (6 instances)
Cache L1i: 384 KiB (6 instances)
Cache L2: 3 MiB (6 instances)
Cache L3: 16 MiB (2 instances)
Węzłów NUMA: 1
Procesory węzła NUMA 0: 0-11
Vulnerability Gather data sampling: Not affected
Vulnerability Itlb multihit: Not affected
Vulnerability L1tf: Not affected
Vulnerability Mds: Not affected
Vulnerability Meltdown: Not affected
Vulnerability Mmio stale data: Not affected
Vulnerability Retbleed: Mitigation; untrained return thunk; SMT vulnerable
Vulnerability Spec rstack overflow: Mitigation; Safe RET
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2: Mitigation; Retpolines; IBPB conditional; STIBP disabled; RSB filling; PBRSB-eIBRS Not affected; BHI Not affected
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Not affected